Semiconductor wafers are commonly used in the production of integrated circuit (IC) chips on which circuitry are printed. The circuitry is first printed in miniaturized form onto surfaces of the wafers. The wafers are then broken into circuit chips. This miniaturized circuitry requires that front and back surfaces of each wafer be extremely flat and parallel to ensure that the circuitry can be properly printed over the entire surface of the wafer. To accomplish this, grinding and polishing processes are commonly used to improve flatness and parallelism of the front and back surfaces of the wafer after the wafer is cut from an ingot. A particularly good finish is required when polishing the wafer in preparation for printing the miniaturized circuits on the wafer by an electron beam-lithographic or photolithographic process (hereinafter “lithography”). The wafer surface on which the miniaturized circuits are to be printed must be flat. Typically, flatness of the polished surfaces of the wafer are acceptable when a new polishing pad is used on the wafer, but the flatness becomes unacceptable as the polishing pad wears down over the course of polishing many wafers. Similarly, flatness and finish are also important for solar applications.
The construction and operation of conventional polishing machines contribute to the unacceptable flatness parameters. Polishing machines typically include a circular or annular polishing pad mounted on a turntable or platen for driven rotation about a vertical axis passing through the center of the pad. A polishing slurry, typically including chemical polishing agents and abrasive particles, is applied to the pad for greater polishing interaction between the polishing pad and the surface of the wafer. This type of polishing operation is typically referred to as chemical-mechanical polishing or simply CMP.
During operation, the pad is rotated and the wafer is brought into contact with the pad. As the pad wears, e.g., after a few hundred wafers, wafer flatness parameters degrade because the pad is no longer flat, but instead has a worn annular band forming a depression along the polishing surface of the pad. Such pad wear impacts wafer flatness, and may cause “dishing” or “doming”.
As illustrated in FIG. 1, “doming”, results in the wafer 50 having a generally convex polished surface 52. This results when the worn pad removes less material from the center of the front surface of the wafer 50 than from the areas closer to the wafer's edge 54. This is because the worn pad's removal rate is inverse to its wear. In other words, the portions of the worn pad with less wear remove more material than portions of the worn pad with more wear. The least amount of material is removed from the wafer 50 by the portion of the pad corresponding to the worn annular band. As a result, the polished wafer has a generally “domed” shape.
As illustrated in FIG. 2, “dishing” results in the wafer 60 having a generally concave shape. One potential reason for this occurring is that the polishing pad becomes embedded with abrasives (i.e., colloidal material from the slurry, debris from previously polished wafers, debris from a retaining ring) causing the removal rate to increase in the areas of wear. The portions of the pad with more wear remove more material from the wafer during the polishing process than portions of the pad with less wear. As a result, more material is removed from the center of the wafer 60 than from its edge 64 resulting in the polished surface 62 of the wafer having a generally “dished” shape.
When the flatness of the wafers becomes unacceptable (e.g., too “domed” or too “dished”), the worn polishing pad has to be replaced with a new one. Frequent pad replacement adds significant costs to the operation of the polishing apparatus not only because of the number of pads that need to be purchased, stored, and disposed of, but also because of the substantial amount of down time required to change the polishing pad.
Accordingly, there is a need for a polishing apparatus that has the ability to optimize flatness parameters by measuring one wafer before and after polishing to determine a removal profile and applying the removal profile to another wafer before polishing.
This Background section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.